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Silicon-on-Sapphire (11-02, R Plane )
Silicon-on-Sapphire (11-02, R Plane )
Silicon on sapphire (SOS) is a hetero-epitaxial process for integrated circuit manufacturing that consists of a thin layer (typically thinner than 0.6 micrometres) of silicon grown on a sapphire (Al2O3) wafer. SOS is part of the silicon-on-insulator (SOI) family of CMOS technologies. SOS is primarily used in aerospace and military applications because of its inherent resistance to radiation.
Silicon EPI Layer:
- Silicon Orientation: (100)
- Type, Dopant: Intrinsic type, undoped
- Silicon Thickness: (0.5 um/0.6 um/1.0 um) +/- 10%
- Resistivity: > 100 ohm.cm
- Micro-particle density ( for particles > 2 um) < 2/cm^2
Sapphire Wafer (Round, Number 1-6) Specifications:
- R plane -- (1-102) with a single flat
- Purity: 99.996%
- Wafer size: 100 mm dia x 0.46 mm thickness
- Flat : One flat 32.5mm +/-2.5mm, at 45+/- 1 deg CCW from <C> on <R>
- Front surface: Epi-polished (Ra < 4nm)
- Back surface: Fine ground
- TTV < 15 um, Bow < 20 um, Warp < 20 um, Flatness (TIR) < 12 um, with Laser Mark on wafer backside, just below the Flat
Sapphire Wafer (Square, Number 7-12) Specifications:
- R plane -- (1-102) with a single flat
- Wafer size: 5x5 x 0.46 mm thickness / 10x10 0.46 mm thickness
- Front surface: Epi-polished (Ra < 4 nm)
- Back surface: Optical grade polish
- TTV < 15 um, Bow < 20 um, Warp < 20 um, Flatness (TIR) < 12 um
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